1

Topic: How do I start porting?

Hi,
I implemented ZX Spectrum on an Altera DE1 board and would like to add esxdos to it. How do you suggest I start with it?
I could not find the esxdos sources (are they public?) which could show the exact hardware requirements in terms of the pins, memory map etc. I would just like to map SD Card to it for the moment.

Can you help me get started?
Thanks!

2

Re: How do I start porting?

gdevic wrote:

Hi,
I implemented ZX Spectrum on an Altera DE1 board and would like to add esxdos to it. How do you suggest I start with it?
I could not find the esxdos sources (are they public?) which could show the exact hardware requirements in terms of the pins, memory map etc. I would just like to map SD Card to it for the moment.

Can you help me get started?
Thanks!

Hi,

You need to implement the "DivMMC" hardware specification, which is a DivIDE with SD/MMC instead of IDE ports, and 128k up to 512k instead of 32k. More info about the DivIDE:

http://baze.au.com/divide/files/pgm_model.txt

Info about SD/MMC ports:

SPI_PORT       equ $EB
OUT_PORT      equ $E7         ; port for CS control (D1:D0)

3

Re: How do I start porting?

Thank you for the link! That document seems to contain what is needed.

I will post result when it's done. I am adding it to the new Z80 model I wrote, described at www.baltazarstudios.com

Thanks!

4

Re: How do I start porting?

gdevic wrote:

I will post result when it's done. I am adding it to the new Z80 model I wrote, described at www.baltazarstudios.com

That's most interesting, specially the A-Z80!

5

Re: How do I start porting?

You may want to check the sources of the ZX Spectrum core inside the ZX-Uno clone. It already implements a complete DivMMC interface.
Tech wiki: http://www.zxuno.com
SVN repo: http://guest:zxuno@www.atc.us.es/svn/zxuno

I'd like to add your A-Z80 to the ZX-Uno but my design flow doesn't support SystemVerilog. Is A-Z80 ported to either VHDL or plain Verilog? The T80 core is fine, but differs at some timmings.

6

Re: How do I start porting?

McLeod, I've seen ZX-Uno that you did - congratulations, it s a *very* neat project!

About 90% of all A-Z80 source files are already Verilog (pre-compiled from the schematic files): all *.v files from folders (alu,bus,registers,control). It is those few exceptions for which I am not sure how difficult it would be to port them from SystemVerilog:
bus/bus_switch.sv - probably very easy
control/execute.sv (+ exec_module.i) ?
control/pla_decode.sv - this one is generated by the z80_pla_checker tool; likely easy
toplevel/z80_top_direct_n.sv (+ core.i) - this is the main module; ?

The rest of the *.sv files in directories are mostly tests and not needed. So, there are not too many files! One would just have to go ahead and start removing sv specifics and tokens and see where the road bumps are. I suspect there would be no hard show-stoppers since I did not use sv in its full potential but mostly to improve readability.

I am not familiar with the Xilinx toolchain, but I am very surprised that they don't support sv!?

7

Re: How do I start porting?

I have updated the project and copied all CPU files into a separate folder called "deploy" so it's easier to pick them up and synthesize the CPU. I will also look into porting those few remaining SystemVerilog files to Verilog, so hopefully you can use it in zxuno and others might benefit. Just need to find some time..