McLeod, I've seen ZX-Uno that you did - congratulations, it s a *very* neat project!
About 90% of all A-Z80 source files are already Verilog (pre-compiled from the schematic files): all *.v files from folders (alu,bus,registers,control). It is those few exceptions for which I am not sure how difficult it would be to port them from SystemVerilog:
bus/bus_switch.sv - probably very easy
control/execute.sv (+ exec_module.i) ?
control/pla_decode.sv - this one is generated by the z80_pla_checker tool; likely easy
toplevel/z80_top_direct_n.sv (+ core.i) - this is the main module; ?
The rest of the *.sv files in directories are mostly tests and not needed. So, there are not too many files! One would just have to go ahead and start removing sv specifics and tokens and see where the road bumps are. I suspect there would be no hard show-stoppers since I did not use sv in its full potential but mostly to improve readability.
I am not familiar with the Xilinx toolchain, but I am very surprised that they don't support sv!?